Architecture

The folowing document describes the overal architecture of our MicroProcessor. Its architecture is heavily inspired of the Sparc Microprocessor but is constrained by the real hardware the thing will run on. ie: an FPGA chip. The instruction set is detailed in this other document. Our work on development tools is detailed there. The internal signals are documented there.

Memory constraints

The microprocessor's general purpose registers are implemented in two of the FPGA RAM bank. 2 RAM banks are used for the program data and the 2 last RAM banks are used for the program itself. Each RAM bank is 8 bit/256 bytes big. ie: each RAM bank can be accessed with an 8 bit data bus.

Register banks

The register banks are configured to be used as dual-port RAM. This allows us to perform a write and a read on each bank at the same time. The idea is that both banks contain the same registers (ie: the same data). Then, during one clock cycle, you can perform the same write in both banks (so that both banks stay synchronized) and two different reads on the two banks. The above arrangement allows us to perform 2 reads and 1 write on the microprocessor's general registers during one clock cycle.

Data RAM

The Data RAM is simply configured so that we can access all the 256*2=512 bytes of memory. We thus access to the Data RAM with an address coded on 9 bits.

Program RAM

The program RAM is configured just like the Data RAM. However, the program RAM behaves for the application programmer as a 256 word sized memory. The address for the program RAM for the application programmer is thus coded on 8 bits.

Microprocessor

The folowing diagram summaries the overall arrangement of the microprocessor and its memory.

The procesor itself can be see on a first view as follows:

Pipeline

0123 4567 8
IF1IF2 IF1IF2 IF1IF2 IF1IF2IF1
IDEEX IDEEX IDEEX IDEEX IDE
WB RF1
RF2		 WB RF1
RF2		 WB RF1
RF2		 WB RF1
RF2		 WB

The above pipeline works as folows: